Gate-All-Around FET (GAAFET) is a type of semiconductor three-dimensional transistor that is considered an evolution over FinFET (Fin Field-Effect Transistors). The comparison of GAAFET vs FinFET marks an advancement in multigate transistors, shifting the conducting channel from vertical fins to nanosheets.
FinFETs, the first three-dimensional transistor that was introduced by Intel in 2011, came up as an advancement from traditional planar transistors (MOSFETs). Below the 28nm process node, planar MOSFETs start to face issues like current leakage, heat dissipation problems and short channel effects. FinFETs managed to solve these issues by adding a vertical “fin” to the gate.
As chip dimensions keep scaling down following Moore’s Law, they need to accomodate more transistors within a given area. At certain scale FinFETs have begun to show similar problems to those experienced by MOSFETs one decade ago. When fins get too close to each other, the risk of leakage currents between adjacent fins increases. This increases power consumption and makes it difficult to maintain control of the transistor when it is in off-state, leading to higher power consumption and lower energy efficiency.
In addition, as the fin width decreases in order to accomodate more transistors, the effectiveness of the gate in controlling leakage decreases, a phenomenon known as “gate leakage”. The gate electrode wraps the fin structure on three faces, but in the bottom face the channel is exposed to the silicon substrate and this can lead to leakage current. Thinner fins also lead to higher resistance, which makes it difficult to maintain proper electrostatic control.
GAAFET aims to solve these issues by switching from vertical fins to nanosheets.
Below the 5nm process node GAAFETs will substitute FinFETs, replacing the vertical fin with “nanosheets”. In a GAAFET the source and the drain are no longer part of a fin but are instead implemented through horizontally stacked nanosheets. While in FinFETs the conducting channel has three contact surfaces, in GAAFET the transistor´s gate fully wraps the four faces of each nanosheet, hence the name gate “all-around”. The bottom face of each nanosheet is fully wrapped by the gate and not in contact with the substrate anymore. This allows for better electrostatic control of the transistor and will allow for further shrinking of semiconductor patterns. It is expected that gate-all-around transistors will be used for the most advanced semiconductor devices until the end of this decade.
Samsung’s 3-nanometer process node is already using GAAFET technology to manufacture integrated circuits. According to Samsung, its gate-all-around technology consumes 45% less power and has a 16% smaller surface area compared to its previous 5nm process. TSMC´s N2 Nanosheet technology will also use GAAFET technology and will commence high-volume manufacturing between 2025 and 2026. TSMC expects a 25%-30% power reduction at same speed and 15% higher chip density when compared to its previous process N3.
GAAFET technology does however come with its own challenges, mainly more manufacturing complexity and higher cost. This is one of the reasons why GAAFET will only be used for cutting-edge chips used in mobile devices or high-performance computing (HPC) applications.
The etching process is a field that becomes much more complex in GAAFETs vs FinFETs. In gate-all-around, multiple etching steps might be required to achieve the desired gate shape and dimension. Once the gate is formed, subsequent etching steps might be required to fine-tune transistor shape or remove sacrificial material without damaging other IC layers.
The deposition process is also more precise and will require more advanced equipment. While in older transistor structures chemical vapor deposition was a very commonly used deposition approach, GAAFET will require atomic layer deposition (ALD). ALD is more precise as it applies the chemical reactants step-by-step, creating deposition films one-atom thick, which results in much smoother surfaces and less probability of microbumps.
The metal pitch refers to the distance between the centers of two adjacent metal interconnect lines on an integrated circuit (IC). Since transistors evolved into 3D strucrures, this measurement has lost significance.
Built directly into the silicon, through silicon vias (TSV) facilitate 3D IC integration and allow for more compact packaging. They have become the default solution to interconnect different chip layers or to stack chips vertically.
Silicon carbide (SiC) is used in electric vehicles due to its wide bandgap and great thermal conductivity. Gallium nitride (GaN) shares many characteristics with SiC while also minimizing RF noise.
The move to CFET vs GAAFET marks a switch from horizontally stacked transistors to vertically stacked ones. This will allow further shrinking of semiconductor patterns and the advancement of Moore´s Law.
GAAFET vs FinFET marks an advancement in multigate transistors, shifting the conducting channel from vertical fins to nanosheets.
FinFETs are three-dimensional transistors with vertical fins that solve most of the problems related to planar MOSFET, such as leakage current or short channel effects.
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