Gate-All-Around FETs (GAAFET) are a type of semiconductor transistor that is considered an evolution over FinFETs (Fin Field-Effect Transistors). The comparison of GAAFET vs FinFET marks an advancement in multigate transistors, shifting the conducting channel from vertical fins to nanosheets.
FinFETs, the first three-dimensional transistor, came up as an advancement from traditional planar transistors (MOSFETs) in 2014. Below the 28nm process node, planar MOSFETs start to face issues like current leakage, heat dissipation problems and short channel effects. FinFETs managed to solve these issues by adding a vertical “fin” to the gate.
As chip dimensions keep shrinking, FinFETs have begun to show similar problems to those experienced by MOSFETs one decade ago. As the transistor metal pitch shrinks (the distance from one transistor´s gate to another), the fins get too close to each other, increasing the risk of leakage currents between adjacent fins. This increases power consumption and makes it difficult to maintain control of the transistor when it is in off-state, leading to higher power consumption and lower energy efficiency.
GAAFET aims to solve these issues by switching the vertical fin with nanosheets.
Below the 5nm process node GAAFETs will substitute FinFETs, replacing the vertical fin with “nanosheets”. The source and the drain are no longer part of a fin but are instead implemented through horizontally stacked nanosheets. While in FinFETs the conducting channel has three contact surfaces, in GAAFET the transistor´s gate fully wraps the four faces of each nanosheet, hence the name gate “all-around”. This allows better control of the transistor and further shrinking of semiconductor patterns.
Samsung’s 3-nanometer process node is already manufacturing semiconductors using GAAFET technology, which reportedly consumes 45% less power and has a 16% smaller surface area. However, manufacturing yields are still not optimal, and it is rumored it has only been used for a small number of chips. TSMC´s N2 Nanosheet technology will also use GAAFET technology and will commence high-volume manufacturing between 2025 and 2026.
GAAFET technology will be used for cutting-edge chips in mobile and high-performance computing (HPC) applications. Semiconductor foundries will require new equipment tools to enable the production of chips using GAAFET architectures.
Built directly into the silicon, through silicon vias (TSV) facilitate 3D IC integration and allow for more compact packaging. They have become the default solution to interconnect different chip layers or to stack chips vertically.
Silicon carbide (SiC) is used in electric vehicles due to its wide bandgap and great thermal conductivity. Gallium nitride (GaN) shares many characteristics with SiC while also minimizing RF noise.
The move to CFET vs GAAFET marks a switch from horizontally stacked transistors to vertically stacked ones. This will allow further shrinking of semiconductor patterns and the advancement of Moore´s Law.
GAAFET vs FinFET marks an advancement in multigate transistors, shifting the conducting channel from vertical fins to nanosheets.
FinFETs are three-dimensional transistors with vertical fins that solve most of the problems related to planar MOSFET, such as leakage current or short channel effects.
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