Prior to the 1980s wire bonding was the main interconnection technique for integrated circuits. Although reliable and still used in many chips, wire bonding results in large form factors, low-density interconnections and less reliability if compared to more modern approaches. With the appearance of 3D ICs, IC interconnection has become part of the semiconductor manufacturing process itself by using through-silicon vias. Built directly into the silicon substrate with etching techniques, through-silicon vias (TSV) facilitate 3D IC integration and allow for more compact packaging. They have become one of the default solution to interconnect different chip layers or to stack chips vertically.
Logic integrated circuits beyond the 28nm process node are designed with 3D structures and have dozens of lithography layers. The deepest layers often contain the building blocks of circuitry such as logic gates and transistors, and this is where the most critical computational tasks are done. The deepest layers normally require extreme ultraviolet lithography (EUV), where the chip is exposed to a ray of light that prints the nanometer transistors into it. However deep layers need to communicate with more superficial ones where other peripheral functions of the IC reside: think of power management, clock distribution or thermal management circuits.
IC layers can communicate between them with through-silicon vias (TSV). TSVs are vertical electrical connections that pass through the silicon substrate, connecting different layers of the IC and allowing information to travel through the different levels. TSVs enable vertical stacking as they reduce the distance between different functional blocks of the chip, resulting in smaller chip packages, higher data bandwidth and lower power consumption. They are an alternative to more traditional interconnection techniques like wire bonding or flip chip.
The continued advancement of Moore’s Law requires chips to improve power per unit of area. Devices like smartphones have important size restrictions, so it is paramount to reduce chip size to the maximum. By building vertical interconnections in the body of the chip directly, through-silicon vias allow for smaller ICs or chip packages while improving data transfer. TSVs facilitate 3D IC integration and allow for more compact packaging.
One of the main challenges of TSV manufacturing is its high aspect ratio, as vias can be more than 100 micrometers deep but only a few micrometres wide. Achieving uniformity and consistency in these structures is challenging as any variation during the etching or deposition processes can lead to uneven electrical performance.
Once the TSV structure is etched, an insulator is added to the via by using an oxide layer, normally silicon dioxide (SiO2). The main purpose is to isolate the silicon substrate from the conductive material that will go inside the via, as without isolation a short-circuit could happen. The oxide layer must be uniform with the same thickness in every part to ensure consistent insulation across the whole via. Temperature must also be controlled, as high temperature can create metal diffusion, with the conductive metals of the vias spreading out into the silicon substrate, rendering the chip unusable. Metal expansion can also add mechanical stress to the semiconductor, so the expansion must be within tolerable limits. Once the insulation and barrier layers are in place, vias are filled with a conductive material, normally copper, which will conduct electricity between the different IC layers.
Through-silicon vias (TSVs) are integrated into the semiconductor manufacturing process flow at various stages: at the outset (via first), in the middle (via middle), or towards the end (via last).
Via-first: It is the simplest approach, as TSVs are one of the first steps in the fabrication process and are manufactured before active devices like transistors. The via-first approach uses conventional semiconductor manufacturing techniques like etching and oxidation without interfering with other IC structures.
One of the main challenges of via-first is that the vias are already built when you reach the front-end process, where high temperatures are applied. The metal filling used to conduct current through the vias can melt and spread out onto the silicon substrate. This issue is known as “via protrusion” and can lead to short circuits or poor device performance. To prevent metal diffusion barrier layers are often used, consisting of thin film materials like tantalum (Ta), titanium (Ti) or tungsten (W). These materials possess high resistance to diffusion and serve as a barrier between the filled metal into the via and the silicon substrate.
Via-middle: the vias are built in the middle of the semiconductor manufacturing process, between the front-end process (manufacturing of the transistors) and the back-end. One advantage is it avoids the challenges related to the front end, where high temperatures can cause metal diffusion in the via. Via-middle adds complexity as it requires perfect alignment and coordination between the front-end and back-end processes. It is also more expensive than via-first as it requires more planning and more specialized equipment and materials.
Via-last: the TSVs are created in the last steps of the semiconductor process flow, after the front-end and back-end. The main advantage of this approach is that it reduces the risk of introducing mechanical stress into the TSVs given they are the last step. There might be alignment challenges given the vias must be aligned with all the existing chip features and there may be limited space and a lot of constraints to etch the TSVs. This approach reduces flexibility in the chip design process.
Built directly into the silicon, through silicon vias (TSV) facilitate 3D IC integration and allow for more compact packaging. They have become the default solution to interconnect different chip layers or to stack chips vertically.
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