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Evolution of Metal Pitch in Semiconductor Transistors

The metal pitch refers to the distance between the centers of two adjacent metal interconnect lines on an integrated circuit (IC). It equals the sum of 1) the metal line width, also known as critical dimension (CD) and 2) the spacing between adjacent metal lines.

The 1) critical dimension refers to the resolution of the printed patterns, basically the smallest pattern that a photolithography machine can print on a chip. CD can be obtained using the Rayleigh equation for semiconductors, which equates to:

Resolution = k1 * λ (wavelength) / Numerical Aperture (NA)

Where k1 is a constant determined by multiple physics and chemical factors, lambda is the wavelength of the light source used, and the numerical aperture (NA) is an optics parameter.

k1 is a constant determined by multiple physics and chemical factors whose physical limit is around 0.25, and most photolithography machines are already close to it. λ (lambda) is the wavelength of the light source. Shorter wavelengths print smaller features. For instance, deep ultraviolet light uses a 193nm light, while extreme ultraviolet, used for the most advanced semiconductors, uses 13.5nm light. Numerical aperture (NA) is an optics parameter of the lens system used in the photolithography equipment, which determines the range of angles over which the system can receive or emit light. Higher NA results in a lower CD or resolution.

The 2) spacing refers to the distance between adjacent metal lines or critical dimensions. This space is required to prevent electrical interference between metal lines.

Although the metal pitch is still widely used in the industry as a measurement of process node evolution in semiconductors, it has lost significance in the last 15 years since transistors evolved to 3D structures.

When transistors were still planar, the gate length and the half-metal-pitch were almost the same distance, and logic node scaling made reference to this measurement. So the metal pitch was still a very relevant measurement that referred to a specific dimension of the IC. However, as pitches kept shrinking due to the advancement of Moore’s Law, transistor structures started to get too close to each other, increasing the risk of leakage current. Leakage current increases power consumption and makes it difficult to maintain control of the transistor when it is in off-state, leading to higher power consumption and lower energy efficiency.

The industry then changed to 3D transistor structures. In 2011 Intel introduced the FinFET transistor, where the channel includes a vertical fin, and in 2024 the industry began transitioning to gate-all-around transistors, where several nanosheets are stacked on top of each other. Under these new 3D architectures the metal pitch has lost significance, as semiconductor logic nodes like 5nm or 3nm do not refer to the half metal pitch any more. For instance, the 5nm process node has a metal pitch of 28nm and the 3nm process node has a metal pitch of 22nm, showing that the process node terminology that we still use has become largely symbolic. We will have to wait until the industry reaches an agreement to, once again, make reference to a real dimension pertaining to the transistor itself like it used to do in the past.

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